Our 37th Annual Electronics Packaging will be held at 91社区's Innovative Technologies Complex
Session Chairs and Speakers
Session 0: Keynote Speakers - (Benson Chan)
Speaker: Mohsen Mardi (AMD)
Presentation Link
Bio: Mohsen Mardi is Senior Director of Hardware Development at AMD and a recognized semiconductor industry leader with more than 30 years of experience spanning hardware engineering, semiconductor test, product qualification, manufacturing, automation, and technology innovation. He leads global engineering organizations responsible for advanced hardware development, Automated Test Equipment (ATE), New Product Introduction (NPI), manufacturing solutions, and Aerospace & Defense (A&D) production programs.
Throughout his career, Mohsen has developed and deployed innovative technologies that address complex challenges in semiconductor test, manufacturing, and product development. He is a prolific inventor with more than 50 patents, many of which have been adopted across the semiconductor industry. His innovations span semiconductor test methodologies, advanced probing technologies, hardware design, manufacturing solutions, automation, and engineering productivity. He also pioneered one of the industry's first ATE robotic automation solutions for semiconductor testing, helping drive greater efficiency, consistency, and scalability in manufacturing operations. These contributions have improved test coverage, product quality, manufacturing efficiency, reliability, and time-to-market for leading-edge semiconductor products.
At AMD, Mohsen leads multidisciplinary teams focused on delivering advanced test, hardware, and manufacturing solutions that enable next-generation High-Performance Computing (HPC), FPGA, Artificial Intelligence (AI), Adaptive Computing, and Aerospace & Defense technologies. He has played a pivotal role in driving strategic technology initiatives, establishing strong partnerships across the semiconductor ecosystem, and deploying scalable engineering solutions for some of the industry's most complex products and manufacturing challenges.
Title: Mohsen Mardi (AMD) - Addressing Challenges for Next鈥慓eneration HPC Wafer Sorting at Advanced Technology Nodes
Abstract:
Advanced nodes continue to push the limits of wafer鈥憀evel probing, particularly as material transitions alter pad behavior and test performance. While earlier nodes (N7 to N3) relied on aluminum鈥慴ased redistribution layers (RDLs), the high鈥憈emperature deposition process led to significant wafer warpage, creating integration challenges for die鈥憈o鈥慸ie stacking and chiplet architectures. To address warpage, N2 technology introduces copper RDLs; however, copper鈥檚 rapid oxidation after wafer fabrication presents new probing risks. Oxidized copper pads exhibit higher hardness and increased contact resistance, resulting in unstable test contact, longer setup times, and potential wafer or probe鈥慶ard damage due to elevated force or current requirements.
This study seeks to develop an optimized probing approach for N2 devices that improves cycle time, increases test reliability, and reduces overall cost by leveraging existing high鈥憊olume probe鈥憈ip technologies. The goal is to achieve robust electrical contact on oxidized copper surfaces while minimizing mechanical stress and ensuring long鈥憈erm probe鈥慶ard durability. The findings aim to establish a reliable, scalable probing methodology that supports high鈥憊olume manufacturing in next鈥慻eneration logic technologies.
Speaker: William Henry, Peter O'Brien (Tyndall National Institute)
Bio: Bill Henry is CEO of Connect Semiconductor, which is co-founded with Professor Peter O鈥橞rien, Tyndall National Institute, Cork, Ireland. Previously, he founded and was chief commercial officer of InfiniLED , a microLED display spin-out from Tyndall. After InfiniLED鈥檚 acquisition by Meta in 2016, Henry managed teams across the United States and Europe as well as strategic partners in Asia. He held various technology and management roles at Meta including Chief uLED Engineer for the Orion AR glasses prototype. He has a B.Sc in chemistry from DCU and a Ph.D. in phyiscal chemistry (photonics) from DCU as well as approximately 20 patents and ongoing applications.
Title: Connect Semiconductor & Design Rule Standardisation for Packaging At Scale
Abstract: Abstract: Current photonic integrated circuit (PIC) packaging is dominated by serial, package-level assembly processes in which optical and electrical interconnects are completed after the PIC has been mounted in its package. These labour-intensive processes, including active fibre alignment, electrical interconnection, and final package assembly, typically require tens of minutes per device, are difficult to automate, and offer limited manufacturing scalability, with production capacity increasing only through the addition of more packaging equipment. This approach, originally developed for low-volume telecommunications applications presents a manufacturing bottleneck, and is no longer suitable for PIC production environments and emerging PIC mass markets.
This presentation will provide an overview of recent advances in wafer-level photonic packaging, highlighting previous developments, the challenges associated with customised packaging approaches, and the opportunities for scalable packaging through design-rule driven standardisation. I will also discuss the role of the European Pilot Lines in accelerating technology translation and describe the journey from research laboratory innovation to industrial-scale manufacturing and commercialisation.
Session 1: Heterogeneous Integration 鈥 Sathya Raghavan & Aakrati Jain (IBM), Gamal Refai-Ahmed (AMD)
Speaker: Jay Cho (GlobalFoundries)
Presentation Link
Bio: Jay Cho is the 3D Heterogenous Integration manager and a Principal Member of Technical
Staff in Advanced Packaging Lab at GLOBALFOUNDRIES in Malta, NY. He leads pathfinding
development activities for advanced packaging solutions, with a focus on 2.5D and
3D heterogenous integration. Prior to this role, Jay led development efforts in silicon
photonics packaging, CMOS packaging technologies, and OSAT engagement strategies.
Before joining GLOBALFOUNDRIES, he worked for Intel and Dow Chemical for advanced
materials and semiconductor packaging. He received B.S. and M.S. degree from Seoul
National University, South Korea and Ph.D. degree from Georgia Institute of Technology,
Atlanta, GA, USA
Title: Progress and technical barriers in 3D Heterogenous Integration
Abstract:
As Moore鈥檚 Law continues to slow down at the transistor level, advancements in interconnect technologies and advanced packaging have become critical to sustain system-level performance improvements. One of the most promising approaches is 3D heterogeneous integration, which enables the integration of similar or dissimilar dies and wafers into highly optimized systems. This presentation will discuss the latest developments in processes, materials, and integration technologies that are driving the adoption of 3D heterogeneous integration. Key industrial applications will be highlighted, along with the remaining technical challenges that must be addressed to enable high-volume manufacturing and widespread deployment.
Speaker: Santos Kurinec (Rochester Institute of Technology)
Presentation Link
Bio: Santosh K. Kurinec is a Professor of Electrical and Microelectronic Engineering at Rochester Institute of Technology (RIT). She received a doctorate in physics from National Physical Laboratory/University of Delhi, India and pursued Postdoc research at University of Florida. She is a Fellow of IEEE and a Member of the New York Academy of Sciences. She is a guest professor at Technical University of Applied Sciences W眉rzburg-Schweinfurt, Germany. She worked at IBM Watson Research Center as a visiting scholar. Her research is focused on advanced integrated circuit materials and devices, currently on ferroelectric devices. She is investigating energy and chemical consumption in semiconductor manufacturing and offsetting via the use of renewables. Kurinec received the 2012 IEEE Technical Field Award for integrating research in teaching to prepare microelectronic engineers for future challenges. She was inducted in the Women in Technology International Hall of Fame in 2018. She received IEEE Region 1 William Terry Distinguished Service Award, 2022, for IEEE service, research and teaching. In 2024, she was appointed as Vice Chair of IEEE SRC Region 1-3, 7. She has over 130 publications in research journals and conference proceedings. She recently edited books on Energy Efficient Computing & Electronics: Devices to Systems, and Nanoscale Semiconductor Memories: Technology and Applications, and Emerging Photovoltaic Materials: Silicon & Beyond.
Title: CMOS scaling to CFETs
Abstract: Moore鈥檚 Law, six decades ago, set the course of complementary metal oxide semiconductor (CMOS) scaling, and its pace has essentially been dictated by dimensional reduction of device size. Then node-to-node performance improvements at fixed power, based on PPA (power-performance-area) efficiency 鈥 referred to as Dennard scaling started. The strong reduction in gate length and width led to an increase in off state leakage current and lower Ion/Ioff ratio. These short channel effects have driven technology to transition from planar MOSFETs to FinFETs, and recently, to gate-all-around (GAA) nanosheet (NS) transistors for high-performance computing applications. The scaling has led to larger effective widths per unit footprint area. Further promising structures are vertically stacked nanosheets and complementary field effect transistors (CFETs). In a CFET configuration, NMOS with Si channel and PMOS with SiGe channel devices are vertically stacked realized using multilayer epitaxial depositions and selective etchings. These advancements require innovations in device architecture, material & process engineering and design technology co-optimization (DTCO) when combined at standard cell level. These include, among others, advanced interconnect and middle-of-line schemes and the introduction of backside power delivery. Backside power delivery network (BSPDN) aims to address these issues by moving the entire power delivery network (PDN) to the backside of the wafer. This helps separate power rails from signal rails which improves power delivery efficiency, reduces interference between signals, and allows for easier routing of signals. While the electrical and density improvements of CFET are undeniable, the architecture is accompanied by a new variety of challenges. These challenges range from the complexity of fabricating CFET devices as well as the parasistics which present themselves during operation. Additionally, heat dissipation becomes a prominent issue. As more research is conducted on CFETs, more effective solutions will be implemented to address these challenges.
Speaker: Gamal Refai-Ahmed (AMD)
Presentation Link
Bio: Gamal Refai-Ahmed is an AMD Senior Fellow, distinguished alumnus of the University of Waterloo, Executive Technologist, and visiting professor at 91社区. His research and engineering practice areas are the thermal management of electronic and optical packaging, where he developed innovative electronic/optical packaging products at Xilinx, GE Research, AMD, Nortel, Astec-Emerson, Cisco, Ceyba, and ATI Technologies. He is the author of more than 120 technical papers and over 130 international patents/pending patents.
In 2010, Gamal was awarded the Calvin Lecture Award, and in conjunction with this
latest recognition, his ASME Fellow grad was elevated to the ASME Life Fellow. In
2014, he was awarded the R.H. Tanner Industry Leadership Award by IEEE Canada for
his industrial leadership of electronics packaging in Canada.
He was elected as a Fellow in the Canadian Academy of Engineering, in recognition
of his leadership in promoting best electronics packaging and thermal management engineering
practice in Canada. Also, He was elevated to Fellow in IEEE and was elected Fellow
in EIC. He is the recipient of the 91社区 SUNY Presidential Medal. He is a recipient
of the University of Waterloo Professional Medal.
Gamal was an adjunct professor at the University of Toronto and distinguished fellow
at Ryerson University, and visiting faculty at 91社区.
Title: From Chip to AI Factory: A Five-Year Integration Roadmap for Silicon Suppliers, Hyperscalers, and Regional AI Infrastructure
Abstract: Artificial intelligence (AI) infrastructure is moving from accelerator-level optimization toward validated AI-factory capacity. In this regime, peak silicon performance is necessary but insufficient: deployable capacity depends on the coupled behavior of silicon, heterogeneous package, substrate, board, rack, liquid-cooling loop, power train, facility, software observability, service model, and regional infrastructure. This talk proposes a five-year engineering roadmap for converting semiconductor innovation into repeatable AI-factory deployment. The central construct is the validated envelope: a multi-domain operating range in which a chip/package/rack/facility configuration can be manufactured, powered, cooled, serviced, monitored, regulated, and replicated at scale without exposing proprietary design details. The paper defines validated envelopes across thermal, mechanical, electrical, fluidic, manufacturing, serviceability, telemetry, safety, regulatory, and regional-infrastructure domains; maps technology drivers including chiplets, high-bandwidth memory, optical input/output, power delivery, liquid cooling, mechanical reliability, and fleet telemetry; and proposes milestone gates for silicon suppliers, hyperscalers, foundry/packaging/outsourced assembly and test ecosystems, cooling suppliers, standards bodies, and regional policymakers. The roadmap is intentionally framed as a decision and validation framework rather than a device forecast. It argues that the practical unit of AI infrastructure scaling is now the validated chip-to region stack: validate once, replicate many times.
Session 2: Photonics Packaging 鈥 John Mazurowski (Penn State Optical Lab), Colin McDonough (AIM)
Speaker: Sarah Baranowski (AIM Photonics)
Bio: Sarah Baranowski is a Photonics Integration Engineer at AIM Photonics where she specializes in the heterogeneous integration of commercial lasers on 300mm PIC MPW wafers. She has a BS in Chemistry and Mathematics from SUNY 91社区, and a MS in Materials Chemistry from Brandeis University. With more than 10 years of experience in semiconductor device fabrication, her current focus at AIM Photonics scales silicon photonics technologies from early-stage development to manufacturing platforms.
Title: Hybrid InP to Si Photonics Integration: Bonding, Alignment, and Optical Performance
Abstract:
Silicon photonic integrated circuits have the potential to enhance and enable new applications for traditional electronic integrated circuits. One challenge posed to the scaling of photonic packages is incorporating on-chip light sources. Traditionally, light is brought to and from a Si photonic chip using optical fibers. An on-chip light source is critical as scaling continues, particularly for consumer products. This paper will demonstrate a hybrid solution, where externally sourced InP laser chips are bonded to a 300 mm Si photonics wafer and edge coupled directly into waveguides. By integrating lasers during packaging and assembly, we can leverage the best of existing laser fabrication technology without disturbing the Si photonic process flow.
InP distributed feedback (DFB) lasers (1550 nm) are eutectic bonded to a 300 mm Si photonics wafer. The lasers interface with the Si photonics through edge coupling into SiN waveguides within an etched trench designed to align the laser to an edge coupler with high accuracy. Laser placement is measured pre- and post-solder reflow in the x and y wafer axes to monitor the placement accuracy and correlate misalignment to coupling losses.
We use fully automatic inline photonic characterization to assess Si and SiN optical waveguide propagation losses before laser die characterization. Laser die attachment quality is assessed by optoelectronic characterization, measuring key parameters. Finally, we assess the repeatability of the bonding process. In this paper, we present our latest laser die attachment results in a 300 mm silicon-photonic technology, with a focus on process optimization and reproducibility.
Speaker: Zahidur Rahim Chowdhury (Global Foundries)
Presentation Link
Bio: Zahidur Rahim Chowdhury is a Member of Technical Staff in Silicon Photonics Packaging at GlobalFoundries, where he leads Pluggable Optical Plug solutions in Optical Engine. He has more than 15 years of experience in semiconductor device fabrication, process integration, modeling, and characterization. Prior to joining GlobalFoundries, Chowdhury conducted research at the University of Toronto, where he earned his Ph.D. in electrical and computer engineering. His research contributions include the development of novel silicon surface passivation technologies, advanced photovoltaic device concepts, and low-temperature semiconductor fabrication processes. He has authored numerous journal and conference publications and has presented research internationally in North America, Europe, and Asia. His technical expertise spans semiconductor manufacturing, photonics, TCAD simulation, process integration, and scientific computing.
Title: Optical Engine Packaging - Path to High Volume Manufacturing
Abstract: GF's SCALE鈩 (Silicon photonics Co-packaged Advanced Light Engine) platform is the industry's first Optical Compute Interconnect Multi-Source Agreement (OCI MSA)-compliant solution. Designed for next-generation AI scale-up architectures, the platform is engineered to meet and exceed the OCI MSA optical interconnect specifications.
Built on GF's advanced silicon photonics technology, the solution employs both coarse and dense wavelength-division multiplexing (CWDM and DWDM) to enable bi-directional data transmission over each optical fiber. This approach significantly increases bandwidth density and system scalability compared with conventional copper interconnects.
The SCALE Co-Packaged Optics (CPO) platform leverages GF's portfolio of fully qualified photonic devices, including high-speed micro-ring modulators, coupled-ring resonators, and integrated photodiodes. The platform also incorporates advanced packaging technologies such as Through-Silicon Vias (TSVs) for high-speed signal routing and power delivery, along with fine-pitch copper interconnects. Integration of electrical ICs fabricated on advanced process nodes enables optimal co-design of leading-edge compute and state-of-the-art photonic technologies without compromising performance.
While GF supports multiple fiber-attach methodologies, the SCALE solution utilizes broadband detachable fiber interfaces that provide low, flat insertion loss across the CWDM spectrum, ensuring robust and scalable optical connectivity.
This presentation will focus on the packaging architecture of the SCALE platform and outline the path toward high-volume manufacturing of GF's optical engine technology.
Speaker: Amy Van Newkirk (Penn State Applied Research Lab)
Presentation Link
Bio: Dr. Amy Van Newkirk is the head of the Fiber Optics and Photonics department at the Penn State Applied Research Lab, Electro-Optics and Electronics Division. Her primary area of expertise is specialty optical fibers. She currently works in anti-resonant hollow core fibers for defense applications. Van Newkirk is a recipient of the Air Force Office of Scientific Research Young Investigator program. She earned a doctorate at CREOL, the College of Optics and Photonics, at the University of Central Florida, where she investigated a variety of specialty optical fibers for sensing and laser delivery applications. Van Newkirk earned her undergraduate degree in Applied Physics from Grove City College in Grove City, Pennsylvania.
Title: Properties and Applications of Hollow Core Fiber
Abstract: Anti-resonant hollow core fiber is a rapidly developing technology with a wide array of applications areas. This new design of optical fiber enables significant advancements in the areas of communications, sensing, power delivery, and more due to the high confinement of optical power within the hollow core of the fiber. This presentation will cover the optical properties of anti-resonant hollow core fiber and the current state of the art for hollow core fiber design. I will also be presenting a variety of applications for which this fiber is well suited and the latest results from these research areas, including telecommunications, high power laser delivery, and radiation hardness. The benefits of hollow core fiber are accompanied by fabrication and integration challenges, so the presentation will also cover the current state of hollow core fiber fabrication and efforts in connectorizing and splicing.
Session 3: mmWave and 5G Packaging 鈥 Steve Gonya (91社区)
Speaker: Anthony Ngoma (Corning)
Presentation Link
Bio:
Title: Glass for mmWave Applications: A Critical Perspective
Abstract:
Speaker: Tom Rovere (Lockheed Martin)
Bio: Tom Rovere is a Lockheed Martin Fellow for Lockheed Martin Rotary and Mission Systems division in Owego, N.Y. In this capacity, he is responsible for research and development related to flexible hybrid electronics (FHE), printed electronics, antenna manufacturing, circuit card assembly, and secure processing development. His primary role is to mature new technologies, bringing them to production level readiness.
Rovere has earned multiple trade secret awards and patents related to circuit card manufacturing. He has also received Lockheed Martin鈥檚 Evening of Excellence Award for Technical Innovation. He serves as Owego鈥檚 IPC representative, is Lockheed Martin鈥檚 Technical Council Representative for NextFlex, and is on the Surface Mount Technology Association Global Board of Directors. This past year Rovere became a Lockheed Martin Fellow and NextFlex Fellow.
Title: mmWave Phased Arrays for UAVs
Abstract: Commercial millimeter-wave 5G New Radio (NR) technology has been designed to operate in both the sub-6 GHz and millimeter-wave (24 - 100 GHz) bands. The sub-6 GHz band offers lower propagation losses over longer distances and the ability of the signals to penetrate (to a degree) through buildings, foliage, and other obstacles. The millimeter-wave band offers advantages of much higher data rates and low latency compared with sub-6 GHz and the ability to handle a high density of user equipment in a small area; however, the propagation losses are higher, signals may be blocked by walls and other obstacles, and rain. As such, commercial 5G development has been focused on taking advantage of the benefits of each, with sub-6 equipment being used in suburban and rural environments requiring wide coverage, and millimeter-wave being used in high density user areas such as airports, stadiums and city centers.
For military applications, the very high data rate, reduced latency and high-density capability of a millimeter wave 5G would add significant performance benefits to applications such as drone aircraft swarms, synthetic vision/Virtual Reality/Augmented Reality for ground troops, and autonomous vehicles.
Electronically steered phased arrays offer the following advantages over mechanical gimbal steered antennas: 鈥淪oft-failures鈥 (failures of several elements) can have little impact to overall antenna performance due to the large number of elements; the array can be much lower profile without the gimble; steering is accomplished within milliseconds; and multiple beams are supported.
This presentation will describe work from Lockheed-Martin RMS Owego/SunRay Scientific, and Rochester Institute of Technology to developed a low-cost, air-cooled millimeter-wave electronically steered phased array. The array assembly parts and materials are all readily available commercial off-the-shelf. The printed wiring boards are manufactured using industry standard materials and processes.
Overview of the project will be shared along with additional testing data and flight testing.
Speaker: James C. M. Hwang (Cornell University)
Presentation Link
Bio: James C. M. Hwang received the B.S. degree in physics from National Taiwan University, and the M.S. and Ph.D. degrees in materials science and engineering from Cornell University. He is currently a Professor at the Department of Materials Science and Engineering, Cornell University. Prior to that, he spent most of his academic career with Lehigh University, after years of industrial experience at IBM, Bell Labs, GE, and GAIN. He cofounded GAIN and QED; the latter became the public company IQE and remains the world's largest compound-semiconductor epitaxial wafer supplier. He was a Consultant for the U.S. Air Force Research Laboratory, and a Program Officer for GHz-THz Electronics for the Air Force Office of Scientific Research. He was an IEEE Distinguished Microwave Lecturer. He is an IEEE Life Fellow and an Editor of IEEE Journal of Microwaves. He has worked for decades on electronic, optoelectronic, and micro-electromechanical materials, devices, and circuits. He was the recipient of many honors and awards, including the IEEE Lester F. Eastman Award for outstanding achievement in high-performance semiconductor devices. His current research focuses on sub-THz materials, devices, and circuits for next-generation automobile radars, Internet of Space, and 6G wireless communications.
Title: Microwave and Millimeter-Wave Permittivity of High-Thermal-Conductivity and Low-Dielectric-Loss Substrates
Abstract: Despite the complex permittivity, including dielectric constant and loss tangent, being critical to electronic devices and packages, literature is sparse for the permittivity of high-thermal-conductivity and low-dielectric-loss single crystals such as AlN, SiC, and diamond, especially at microwave and millimeter-wave frequencies. Filling in this knowledge gap, we have found AlN to have even lower loss than fused silica鈥揳 traditional low-loss standard. On the other hand, SiC has the lowest loss of all materials we have tested, except diamond at frequencies much higher than 100 GHz. Compared to most mature materials in which the loss increases with increasing frequency due to lattice phonons, the loss of diamond increases with decreasing frequency due to point defects. Therefore, as diamond becomes purer and more perfect, it may utlimately have the lowest dielectric loss and highest thermal conductivity of all single crystals.
Session 4: Flexible, Wearable and Additive Electronics 鈥 Felippe Pavinatto (GE Aerospace). Mark Poliks (91社区)
Speaker: Benyamin Davaji (Northeastern University)
Presentation Link
Bio:
Title: From Data to Device: Physics-Informed Digital Twins for Printed Microsystems
Abstract:
Speaker: Chris Taabor (AFRL)
Presentation Link
Bio: Dr. Christopher Tabor is a Senior Research Scientist within the Materials and Manufacturing Directorate at the Air Force Research Laboratory (AFRL). He leads the Soft Materials and Responsive Technologies Research Team, exploring fundamental and early applied research on soft sensors and electronics, responsive structures, and resilient polymers. After obtaining a Ph.D. in chemistry from Georgia Tech in 2009, he joined AFRL as a National Research Council Fellow before moving to a permanent staff scientist position researching flexible and stretchable electronics, with an emphasis on room temperature liquid metals. Tabor鈥檚 work has been highlighted in the defense technology media on multiple occasions, and he has published over 60 peer-reviewed journal articles with 16 patents.
Title: Encapsulating the Future: Multi-Scale Packaging and Living Matrices for Stretchable Liquid Metal Electronics
Abstract: Liquid metal alloys, such as eutectic gallium-indium (EGaIn), offer unparalleled stretchability for flexible electronics, but their fluidic nature presents significant packaging challenges. This talk explores how multi-scale encapsulation techniques鈥攁nd novel integrations with biological matrices鈥攎aintain device stability and enable new functionalities. (1) At the particle level, coating EGaIn with non-native silica nanoshells creates a chemically inert barrier that increases stiffness and tunes rupture behavior. Encapsulating these particles within coaxial polyurethane nanofibers further prevents leakage while enabling in-situ shear-sintering. (2) At the macro-scale, packaging liquid metal traces with conformable dielectrics like VHB tape or polyurethane preserves signal integrity for high-frequency RF systems under extreme mechanical strains. For wearables, encapsulating networks in electrospun spider silk yields highly breathable, skin-conformal electrodes. (3) Pushing the boundaries of packaging, liquid metal networks can now be integrated with Engineered Living Materials (ELMs), such as yeast-loaded hydrogels. This biological proliferation drives programmed volumetric expansion in the substrate, transfiguring flat 2D substrates into complex 3D forms, such as stretchable helices. Remarkably, this growth-induced strain autonomously activates the liquid metal into a conductive state. Furthermore, these ELM substrates are fully biodegradable, offering a transient and sustainable packaging solution. Ultimately, these diverse encapsulation strategies 鈥 ranging from rigid nanoshells and conformable elastomers to shape-shifting, transient living materials鈥 are essential for transitioning liquid metals into robust and sustainable soft electronic systems.
Speaker: Guha Manogharan (Penn State, ARL)
Presentation Link
Bio: Guha Manogharan is a Professor of Mechanical Engineering at The Pennsylvania State University and Co-Director of the Center for Innovative Materials Processing through Direct Digital Deposition (CIMP-3D). He received his Ph.D. and M.S. in Industrial and Systems Engineering from North Carolina State University. His research focuses on additive and hybrid manufacturing, 3D structural electronics, 3D sand printing, digital casting, multi-material processing, and biomedical applications of additive manufacturing.
Dr. Guha has led federally and industry-sponsored research supported by DARPA, NSF, SEMI-FlexTech, AFRL, ONR, NIST, America Makes, IACMI, and the Commonwealth of Pennsylvania. Recent projects include a $1.6 million DARPA award and a $1.5 million advanced digital casting initiative. His contributions to advanced manufacturing have been recognized through the 2026 ASME Chao and Trigger Young Manufacturing Engineer Award, 2020 NSF CAREER Award, and 2017 SME Outstanding Young Manufacturing Engineer Award. His research advances next-generation manufacturing technologies for electronics, aerospace, defense, biomedical, and industrial applications.
Title: Concurrent Design and Process Planning for the Hybrid Additive Manufacturing of 3D Structural Electronics.
Abstract: Multi-axis hybrid additive manufacturing is enabling a transition from conventional planar electronics toward three-dimensional structural electronic systems in which functional components and electrical interconnects are embedded directly within complex geometries. This enables sensors and electronic components to be distributed throughout a structure in arbitrary orientations, enabling compact multifunctional devices.
Despite this potential, current manufacturing workflows remain limited. Most existing approaches rely on 2.5D or conformal-printing strategies that are restricted to surface-level integration and frequently require manual component placement.
This work presents a concurrent process-planning framework for the automated manufacture of 3D structural electronics. The proposed methodology integrates structural fabrication, electronic component placement, process sequencing, and toolpath planning within a unified workflow. Existing voxelization-based approaches often generate large numbers of discrete buildable volumes, introducing discretization artifacts that degrade boundary fidelity and geometric accuracy. These limitations reduce manufacturability and hinder scalability toward production-level systems.
The framework leverages the multi-tool capabilities of hybrid additive manufacturing systems, including material deposition and automated pick-and-place operations. This enables electronic components to be incorporated during fabrication rather than traditional assembly processes. The framework further addresses key challenges in volumetric circuit architectures, including component accessibility, interconnect routing, tool constraints, and build-sequence optimization.
The proposed methodology establishes a foundation for the scalable manufacturing of multifunctional devices with embedded electronics and complex internal interconnect structures. It enables more compact and highly integrated 3D structural electronic systems. Potential applications include positional sensing, micro-fliers, phased-array antenna systems, and medical devices.
Session 5: Power Electronics / Harsh Environments 鈥 David Shaddock (GE)
Speaker: Nicholas Baker (U Alabama)
Presentation Link
Bio: Nick Baker is an assistant professor at the University of Alabama, USA. He received his doctorate from Aalborg University in 2016, focusing on Junction Temperature Measurements in Power Semiconductor Modules. In 2015, he was awarded the European Power Electronics Young Engineer Award in 2015. In 2015 and 2019, he was a guest researcher at the French Institute of Science and Technology in Versailles, France. From 2019 to 2021, he was an Independent Researcher funded by the Danish Independent Research Fund. His primary research interest is the reliability and manufacturing of power semiconductor interconnects - in particular on the use of liquid-metal based interconnects.
Title: LIME: Liquid-Metal Interconnects for Power Semiconductors and Power Electronics
Abstract: Power semiconductors are vulnerable to thermo-mechanical stress due to the use of solid-metal interconnect processes such as wire bonding, soldering, and sintering. This talk will present Gallium-based liquid-metal pastes for use in chip-level packaging of SiC MOSFETs. All chip critical interconnects (i.e., die-attach, topside, and gate) are implemented using liquid-metals (LIME), which remain liquid throughout semiconductor operation up to 175掳C. Compared to SiC MOSFETs using industry-standard interconnects, LIME packaged SiC MOSFETs exhibit improved thermal performance and demonstrate an increase in power cycling lifetime by potentially a factor of 100x. Notably, LIME interconnects are contained on the chip without the use of any encapsulation material, and are manufactured at room-temperature with no hazardous chemicals. Furthermore, the presentation will show a recycling demonstration of a LIME packaged SiC MOSFET, where a single chip SiC MOSFET is disassembled and repaired multiple times after it reaches end-of-life. Finally, double side cooled module designs (enabled through the use of LIME) that deliver a heat flux of 1000W/cm2 using only 2x 40mm axial fans will be shown.
Speaker: Felippe Pavinatto (GE Aerospace)
Presentation Link
Bio: Dr. Felippe Pavinatto is a Senior Engineer at GE Aerospace employing additive electronics manufacturing to generate new technologies for advanced electronics packaging, harsh environment electronics, inspection probes for services and next generation propulsion systems.
Dr. Felippe Pavinatto is a Material Scientist and Engineer that has been working with additive electronics manufacturing for over 15 years in academia and industry. His expertise is centered on advanced materials, electronic inks and printed electronics technologies. Over the years, Dr. Felippe has employed his advanced manufacturing specialization for developing scalable fabrication processes for flexible hybrid electronics (FHE) in the fields of bioelectronics, energy devices, and wearable electronics.
Since joining GE Aerospace in January 2023, his work focuses on harsh environment electronics and sensors for aerospace applications. Felippe is the principal investigator on projects that explore the use of printed electronics for developing manufacturing process for more integrated devices with reduced size, weight, and power (SWaP). He leads teams of professionals from GE Aerospace and its partners on programs in the following areas: (i) manufacturing of advanced inspection probes for non-destructive evaluation and structural health monitoring (SHM) of jet engines in services operations; (ii) embedded electronics packaging for radiofrequency (RF) and sensing; (iii) harsh environment sensor for defense and next generation propulsion systems.
Dr. Felippe has been committed throughout his career to generating innovative technologies and solutions to meet industrial demands via collaborative and multi-disciplinary research projects. The impact of his research is reflected in the publication of 61 papers in peer-reviewed scientific journals (3415 citation, H-index of 32), 3 book chapters and 10 patents. His industry leadership is also reflected in his recent appointment as the Chair of the IEEE 3D Heterogeneous Integration Roadmap chapter on Additively Manufactured Electronics (AME).
Title: Printed components for high temperature sensors and packaging applications
Abstract: Additively Manufactured Electronics (AME) are emerging as a powerful approach for enabling electronic devices in geometries, materials systems, and operating environments that are difficult or impossible to address with conventional planar microfabrication. At GE Aerospace, we have been investigating direct-write 3D printing methods to produce embedded and conformal electronic functionalities on complex three-dimensional components intended for harsh-environment operation. These approaches open new possibilities for integrating sensing, interconnects, and packaging directly onto structural or high-temperature parts while reducing assembly complexity and expanding design freedom.
This presentation will provide examples of how we have been using printed electronics to produce components and electronics packages for harsh-environment, high-temperature aerospace-relevant applications. First, a brief review of printed passives devices (resistors and capacitors) and interconnects for high temperature operation will be provided. Next, we will describe examples of more complex printed sensor arrays with capability of operating at temperatures of up to 1000 掳C. The talk will end with a description of how GE Aerospace has been using printed electronics technologies to manufacture all-additive embedded-die packaging technologies for RF and harsh environment sensor devices for hypersonics. Together, these examples illustrate how direct-write additive electronics can enable new device architectures and form factors for embedded, conformal, and harsh-environment applications.
Speaker: Ahmad Kirmani (RIT)
Presentation Link
Bio: Dr. Ahmad R. Kirmani is an Assistant Professor of Chemistry & Materials Science at the Rochester Institute of Technology (RIT), New York (US). He directs the Optoelectronic Reliability in Orbital Environments (ORION) laboratory that advances emerging thin-film semiconductors for optoelectronic applications in extreme environments, such as the near-Earth space. Prior to joining RIT in 2023, Dr. Kirmani carried out postdoctoral research at the National Institute of Standards and Technology (NIST) and National Renewable Energy Laboratory (NREL/NLR). He is recognized for advancing halide-perovskite space photovoltaics and led the development of radiation-testing guidelines in 2022. He is a task lead on the SSTI-3 project funded by the US Space Force to develop perovskite solar cells for space power and working with DARPA to advance halide-perovskite radiovoltaics/nuclear batteries. Kirmani also serves as the Associate Editor of APL Energy, a sister journal of Applied Physics Letters.
Title: Lightweight Packaging for Emerging Space Solar Cells
Abstract: Metal-halide perovskites are an emerging class of semiconductors and could meet the power requirements of the proliferating near-Earth space. Perovskite solar cells promise high W/kg at low $/W and have shown notable radiation tolerance. Given their flexible form factors and chemical sensitivity, it is important to develop lightweight encapsulation layers that offer protection from space stressors such as radiation, atomic oxygen, vacuum, and thermal cycling, without adding too much mass to perovskite solar panels. I will present our recently patented technology that utilizes silicon oxide (SiOX) thin films deposited directly on solar cells via thermal evaporation, offering a 100% increase in specific power over conventional cover glass packaging. SiOX barriers protect the solar cells from radiation damage, atomic oxygen stress, and environmental stressors, such as moisture. I will finally discuss on-orbit performance of our perovskite device stack that utilizes SiOX packaging based on a ~100-day CubeSat flight experiment underscoring the promise of ultralight packaging for emerging space PV.
Session 6: Future of Computing for HPC / AI
Speaker: Edmundo Gutierrez (INAOE)
Presentation Link
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Title: Characterization and modeling of CMOS cryogenic reliability for quantum computing
Abstract: This talk introduces the experimental characterization of 65nm, 28nm, and 14nm CMOS technologies down to 4.2 K and below. Special attention is taken at the selfheating mechanism and degradation of electrical parameters. In view of the potential application of CMOS technologies to quantum computing, an electro-thermal and reliability model is proposed.
Speaker: Riley Freeland (Corning)
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Bio: Riley Freeland is a Principal Scientist at Corning Research and Development Corporation in Corning, N.Y. He joined Corning in 2001, and has served as a measurements engineer, analyst, and solution designer. He received a B.S. in engineering physics from Cornell University in 1995, and a doctorate in atomic and molecular optical physics from the University of Texas at Austin in 2001.
Title: Connecting Light to the Chip: Glassworks AI Introduction
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Speaker: Sean Hart (IBM)
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Title: Frontiers of Quantum Computing Infrastructure
Abstract: Continued advances in the scale, quality, and speed of commercial quantum computers have pushed such machines toward an era of quantum advantage, when quantum computers will deliver solutions to practical, real-world computational tasks. This talk will highlight IBM Quantum's leadership in this space, surveying our roadmap to error-corrected quantum computers based on superconducting qubits and the subsystem hardware enabling this scaling. With respect to hardware, we will provide a perspective on critical areas for components and infrastructure development in support of this vision.
Session 7: Substrates, Platform for Advanced Packaging 鈥 David Levy (Mosaic), Sean Garner (Corning)
Speaker: Aric Shorey (Menlo Micro)
Presentation Link
Bio: Aric Shorey is VP Government Affairs and Strategic Market Development at Menlo Microsystems, a company that has introduced a revolutionary Ideal Switch MEMS device based on all glass packaging. Shorey has an MS in mechanical engineering and doctorate in materials science from the University of Rochester. He has driven innovation in areas of materials processing, characterization as well as program management in the microelectronics, precision optics and telecommunications industries for more than 25 years. Most recently, he has focused on establishing glass as a microelectronics substrate.
Title: The Ideal Switch庐: Applications for Glass-based MEMS device with demonstrated reliability
Abstract: Menlo Microsystems has introduced a MEMS switch (the Ideal Switch庐) that utilizes both a glass substrate and a glass cap with through glass via (TGV) technology to provide an all-glass packaging solution. It is the world鈥檚 smallest, most reliable, and efficient micro-mechanical switch that can be used for numerous RF and power applications. The Ideal Switch庐 gains superior performance as well as mechanical, electrical and thermal reliability from several aspects of the MEMS and glass packaging design including robust electrical contacts, low electrical loss of glass, and hermetic TGVs which provide a well-controlled environment. This controlled environment is crucial for attaining reliable performance over billions of cycles. In addition to long lifetimes, parasitics are reduced by >75% vs. Si based RF devices enabling the devices to have a wide operational bandwidth from DC to > 50 GHz.
To enable the volume manufacture of this device Menlo has driven advancements in the glass supply chain over the past several years, leveraging mostly standard semiconductor manufacturing processes, on glass substrates (with and without TGV). In addition to hermetic TGV, the device contains multi-layer plated and deposited structures, hermetic wafer level glass to glass bonding, post-bond die singulation and device packaging in multiple formats. These devices pass standard JEDEC reliability testing and have operational lifetime in excess of 3 billion cycles. In this presentation we will review the Ideal Switch庐, performance characteristics and discuss applications in both RF and emerging power distribution and control.
Speaker: Sule Ozev (Arizona State University)
Bio: Sule Ozev is a professor in the School of Electrical, Computer and Energy Engineering at ASU. She received her B.S. in EE from Bo臒azi莽i University and her M.S. and Ph.D. in CS from UCSD. Before joining ASU in 2008, she was on the faculty at Duke University.
Ozev's research spans electronic design automation (EDA), advanced semiconductor packaging, heterogeneous integration, and test and reliability of integrated circuits and systems. Her current work focuses on design automation for chiplet-based systems, RF and mm-wave design methodologies, digital twin technologies for advanced packages, multiphysics modeling, and chiplet layout automation.
She has led numerous research programs supported by the National Science Foundation, Semiconductor Research Corporation, NASA, IBM, and the U.S. Department of Defense, and is a principal investigator or co-investigator on several national semiconductor initiatives, including SHIELD USA and the Southwest Advanced Prototyping (SWAP) Hub. Ozev is the recipient of the ASU Joseph C. Palais Distinguished Faculty Scholar Award, and over 10 IEEE best paper awards. She has authored more than 200 technical publications.
Title: SHIELD USA and the Next Generation of Advanced Packaging
Abstract: Advanced semiconductor packaging has become a critical enabler of next-generation electronic systems, driving advances in performance, power efficiency, heterogeneous integration, and system functionality. As part of the SHIELD USA initiative, Arizona State University and its partners are working to accelerate U.S. leadership in advanced packaging by developing technologies that bridge innovation, manufacturability, and ecosystem readiness.
This presentation highlights research directions supporting that vision, with a focus on design enablement and package reliability. Topics include methodologies for reliability assessment, design automation and design support tools, and physics-based modeling of package behavior, including warpage, thermal transport, and signal delay. These capabilities are essential for reducing design risk, shortening development cycles, and enabling first-pass success for increasingly complex heterogeneous systems.
A particular emphasis will be placed on advanced substrate technologies that enable arbitrary dielectric and conductor thickness "recipes." This flexibility provides designers with new opportunities to optimize electrical, thermal, and mechanical performance while tailoring RF characteristics to application-specific requirements. The ability to independently engineer layer thicknesses opens new design spaces for impedance control, loss reduction, integrated passive components, and high-frequency performance that are difficult to achieve with conventional substrate manufacturing approaches.
By combining advanced modeling, design automation, reliability engineering, and innovative substrate technologies, SHIELD USA is helping establish the foundational capabilities needed for future generations of high-performance microelectronic systems. The presentation will discuss how these complementary research areas contribute to a more agile, manufacturable, and resilient advanced packaging ecosystem that supports both emerging commercial applications and broader national semiconductor objectives
Speaker: Rachael Gitnes (Tektronix Component Solutions)
Presentation Link
Bio: Rachael Gitnes is an Application Engineer at Tektronix Component Solutions with a background in semiconductor fabrication process engineering. She previously supported inspection-critical manufacturing processes, including wafer-level probe mark analysis and internal package inspection using acoustic microscopy. In her current role, Gitnes bridges technical understanding with customer engagement. When she is not working, she enjoys playing competitive volleyball and spending time outside in Pacific Northwest through hiking with her dog, Woody.
Title: Compliant Gold-bump Grounding for Solderless High-Frequency Connectors on Fused Silica
Abstract: Low-loss substrates such as fused silica support high-frequency signal routing with excellent dielectric performance, but their low fracture toughness creates reliability challenges for direct connector attachment. This paper presents a solderless grounding approach using compliant gold ball-bond bumps as distributed ground contacts for a 110 GHz connector mounted on fused silica. The gold bumps plastically deform during connector installation, providing electrical grounding while reducing direct mechanical loading on the substrate. Initial test vehicles maintained stable RF performance after thermal loading but exhibited localized cracking. Mechanical and electromagnetic simulations were used to optimize bump count, geometry, and placement. The optimized design eliminated cracking after thermal cycling while maintaining insertion loss and return loss performance, demonstrating a practical interconnect approach for reliable mmWave packaging on fragile, low-loss substrates.
Session 8: Thermal Challenges - Ramchandra Kotecha (GE Aerospace) / Srikanth Rangarajan (91社区)
Speaker: Srikanth Rangarajan (91社区)
Presentation Link
Bio: Srikanth Rangarajan works as an assistant professor in the School of Systems Science and Industrial Engineering at 91社区. He received his M.S. and Ph.D. in mechanical engineering from the Indian Institute of Technology Madras in 2017. His research interests include thermal management of electronics digital twinning for electronics thermal management systems, thermal energy storage and data center cooling. Rangarajan leads the thermal section of the IEEE Electronics Co-Design Roadmap chapter. He has published over 44 international journal articles and is also the author of the book "Phase Change Material Heat Sinks: A Multi-Objective Perspective." Rangarajan has received competitive research funding from a broad range of federal and industry-aligned agencies, including ARPA-E, the National Institute of Standards and Technology (NIST), and the Semiconductor Research Corporation (SRC), in support of work on advanced thermal management, digital twins, and AI-enabled engineering systems.
Title: AI for liquid cooling of Electronics
Abstract: The rapid escalation of power density and architectural complexity in modern electronic systems has elevated thermal management to a central challenge for reliability, performance, and sustainability. Artificial intelligence (AI) offers transformative capabilities for addressing this challenge through data-driven modeling, optimization, and predictive control of advanced cooling solutions. However, the effective integration of machine learning into thermal sciences requires coordinated progress across three tightly coupled dimensions: high- quality and representative data, robust and scalable learning algorithms, and faithful representation of complex, multiscale heat-transfer physics. Advances in any single dimension alone are insufficient. This talk demonstrates how image-based metrology serves as a critical enabler for AI by providing rich, high-fidelity visual data that bridges experimental observation and physics-aware learning. The talk further highlights how synergistic developments across data, algorithms, and physics enable trustworthy AI-enabled thermal solutions and serve as a foundation for digital twins, dynamic virtual replicas that fuse real-time data, physics-based models, and AI. Together, these advances unlock new capabilities for system-level monitoring, prediction, and optimization, paving the way toward reliable, energy-efficient, and sustainable electronic systems.
Speaker: Vivian Ryan (Northrup Grumman Corporation)
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Speaker: Theodorian Borca-Tasciuc (RPI)
Presentation Link
Bio: Dr. Theodorian (Theo) Borca-Tasciuc has a B.S. in Physics from Bucharest University and a Ph.D. in Mechanical Engineering from UCLA. He started his academic career in 2001 at Rensselaer Polytechnic Institute and since 2013 he is a full professor. He is the director of the Nanoscale Thermophysics and Energy Conversion Laboratory (NanoTEC) on the Rensselaer campus. His research interests include fundamental and multiscale investigations of thermal transport and energy conversion particularly in solid-state and development of innovative materials, devices, and systems. He received the NSF CAREER award, School of Engineering Outstanding Team award, is a member of the ASME鈥檚 K8 committee on Fundamentals of Heat Transfer, and a member of the ASME's K-9 committee on Nanoscale Thermal Transport. He organized and chaired multiple symposia and sessions on nanoscale thermal transport and energy conversion with ASME, MRS, and CIMTEC International Conferences. Borca-Tasciuc graduated (as main advisor or co-advisor) 20 doctoral students and several dozens of master's students. He authored >100 journal articles, several patents and book chapters, has >10,000 citations, and h-index of 49.
Title: Nanoscale Thermal Transport: From Molecular Interface Engineering to Quantitative Thermal Metrology
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As semiconductor technologies advance toward heterogeneous integration, advanced packaging, and increasingly complex back-end-of-line (BEOL) architectures, thermal transport across thin films and interfaces has emerged as a critical factor governing device performance, reliability, and energy efficiency. This talk highlights recent advances at RPI in both the engineering of thermal pathways and the development of quantitative thermal metrology techniques for nanoscale materials and devices.
The first part of the presentation explores molecular engineering of inorganic interfaces, demonstrating that molecular nanolayers can achieve interfacial thermal conductances exceeding 1 GW m鈦宦 K鈦宦, approaching theoretical limits traditionally associated with epitaxial inorganic interfaces. These findings challenge the conventional view of organic layers as thermal bottlenecks and reveal new opportunities for tailoring phonon transport across hybrid organic-inorganic systems.
The second part focuses on emerging thermal characterization methods. Advances in scanning thermal microscopy are presented, including fluid-immersion operation that significantly enhances thermal coupling and sensitivity for non-contact measurements of thin films and nanoscale structures. Complementary developments in the 3蠅 method are discussed through a rigorous experimental-design framework, enabling optimized extraction of anisotropic thermal conductivities and interfacial thermal resistances in technologically relevant thin films.
Applications to porous and ultra-low-k dielectric materials illustrate how composition, porosity, moisture uptake, and interface quality collectively influence heat transport in BEOL structures. Temperature-dependent studies further reveal the importance of separating intrinsic film properties from interfacial contributions. These advances provide a unified framework for understanding, measuring, and engineering heat flow across interfaces and thin films, enabling improved thermal management strategies for next-generation microelectronics and packaging.